Improved LDPC Decoding with Belief Enhancement Node Processor
| Autor: | Cheng-Kang Li, 李政鋼 |
|---|---|
| Rok vydání: | 2010 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 98 Low-Density Parity-Check (LDPC) codes have received great attention in last decade owing to their capacity-approaching performance. The well-known sum-product algorithm (SPA) achieves very good coding gain but it is too complex for hardware implementation. To solve this problem, several approximated algorithms such as scaling min-sum (SMS) are proposed. However, SMS suffers from the performance degradation compared to SPA. Thereby, in this thesis we try to propose a modified scaling min-sum algorithm. Our algorithm improves the coding performance by enhancing the belief propagated conditionally during decoding process. We also propose and implement the serial hardware architecture of our proposed algorithm. Simulation result shows we can obtain about 0.75dB coding gain while BER=10-7 in 80216e and about 0.8dB coding gain in 802.11n. The FPGA implementation result shows that our architecture only adds 3.6% hardware cost. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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