An 8-bit Successive Approximation ADC with Binary Switch Array Capacitor Technique
| Autor: | Yu-Wei Huang, 黃郁偉 |
|---|---|
| Rok vydání: | 2010 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 98 This thesis designs an analog-to-digital converter (ADC). The architecture is an 8-bit Successive Approximation ADC with Binary Switch Array Capacitor Technique, and the sample rate of the circuit achieves 1MSample/s based on a TSMC 0.35μm Mixed-Signal 2P4M Polycide 3.3V manufacturing process. The Chip area of the first SAR-ADC is 1925μm×1579μm, and the supply voltage is 3.3 volts. The measured results are as follows when clock frequency is 1MHz, sample rate is 100KHz, and input frequency of Sine wave is 10KHz (amplitude is 0V~2.4V): Its Differential Non-Linearity error (DNL) is -1LSB~72.986LSB, Integral Non-Linearity error (INL) is -86.961LSB ~ 25.296LSB, SNDR=14.05dB, ENOB=2.04bits, and the whole power consumption is approximately 3.287mW. The chip area of the second SAR-ADC is 1295μm×1120μm, and the supply voltage is 3.3 volts. The measured results are as follows when clock frequency is 1MHz, sample rate is 100KHz, and input frequency of Sine wave is 10KHz (amplitude is 0V~2.4V): Its Differential Non-Linearity error (DNL) is -1LSB ~ 9.132LSB, Integral Non-Linearity error (INL) is -7.364LSB ~ 20.255LSB, SNDR=27.5dB, ENOB=4.28bits, and the whole power consumption is approximately 2.566mW. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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