The Fabrication and Electrical Characterization of MOS Capacitors Using Si- and Zr-doped CeO2 as the High-k Gate Dielectrics
| Autor: | Yi-Kuan Chen, 陳奕全 |
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| Rok vydání: | 2010 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 98 In this work, metal-oxide-semiconductor (MOS) capacitors with a high-k cerium zirconate (CeZrO4) and cerium silicon (CeSiO4) as the gate dielectrics have been fabricated. High-k CeZrO4 and CeSiO4 were fabricated by using CeO2 and zirconate and silicon targets during sputtering process. The addition of Zr and Si in the CeO2 was positionally controlled using the co-sputtering technique. The post-annealing was performed at 550℃, 650℃, 750℃, and 850℃ after thin film deposition. The physical properties were investigated by the TEM and XRD analysis. The electrical properties of different doping locations were compared. The dielectric constant and flatband voltage shift (ΔVFB) as functions of annealing temperature and gradient condition were discussed. The temperature-dependent current of CeO2 and CeZrO4 were compared. As for the Zr-doped CeO2 the leakage current is about 1-2 orders of magnitude less than that of CeO2. The results are consistent with our C-V measurements. The maximum of relative dielectric constants is 16.1 for CeZrO4 (7 nm) after 850℃ anneal. The maximum of relative dielectric constant is 18.5 for CeO2 (4 nm)/CeZrO4 (3 nm) after 850℃ anneal. Secondly, the CeSiO4 layer is firstly deposited on Si. However, the flatband voltage shift shows better for CeSiO4/CeO2/Si structure due to lattice mismatch. The leakage current density of Si-doped CeO2 is 6 x 10-6 A/cm2 obtained at +3 V and -3 V biases for CeO2 (4 nm)/CeSiO4 (3 nm) after 850℃ anneal. The maximum of relative dielectric constant is 14.2 for CeO2 (3 nm)/CeSiO4 (4 nm) after 750℃ anneal. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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