Redundant Via Insertion with Wire Shifting for Yield Improvement
| Autor: | Lee,Sheng-Hung, 李勝弘 |
|---|---|
| Rok vydání: | 2010 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 98 According to the development curve in Moore’s law, the number of transistors is increased doubly every eighteen months. With the increase of design complexity in the fixed area of entire IC, the quality of IC manufacture is decreased. Furthermore, designers have to face more and more challenges in yield issue. There are many factors affecting the yield during IC manufacture. One of the major factors is the failure of routing vias. Currently, the methodology of redundant via insertion has been developed to improve the chip yield in industry. In general, the redundant vias are inserted in the post routing phase, the efforts will be limited by using the remaining routing resource. Therefore, it is necessary to develop an effective redundant via insertion approach with the ability of adjusting the layout to improve the yield. In order to solve the problem of the inserting redundant vias, we propose an effective approach to insert the redundant vias. Firstly, a wire shifting approach is proposed to evaluate the possibility of wire adjustment for single routing via and increase the available positions of redundant vias. Furthermore, based on the yield computation in a Poisson model an efficient two-phase insertion approach is proposed to insert feasible redundant vias to improve the chip yield. The experimental results show that our proposed approach improves the chip yield 17.3% on the average for the tested examples. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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