Hybrid Sigma-Delta Modulator with Digital Error Truncation
| Autor: | Wen-Lin Yang, 楊文霖 |
|---|---|
| Rok vydání: | 2008 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 97 Sigma-delta analog-to-digital converters (ADCs) are traditionally used in instrumentation, voice, and audio applications that require low signal bandwidth and high resolution. In recent years, there has been a growing trend to move ADC towards the system front-end. Due to the scaling in VLSI technology, high performance digital systems can be realized. The ADC has to provide a higher dynamic range for the interface between analog and digital data. Therefore, sigma-delta ADCs which can achieve high resolution with wide input bandwidth for wireless and wireline communication systems becomes more and more important. In this thesis, the design flow of the continuous-time (CT) modulator is presented and a 100MHz CT single-bit active-RC sigma-delta modulator with 1MHz signal bandwidth for Bluetooth application is implemented. The design has been fabricated by TSMC 0.18μm CMOS process. The measured SNDR is 56.8dB and the dynamic range is about 60dB. The power consumption is about 22.2mW at 1.8V supply. The other sigma-delta design is to combine the advantages of the CT and discrete-time (DT) modulators. It is a hybrid sigma-delta modulator with digital error truncation. The work is designed in TSMC 0.13μm CMOS process. The simulation result shows 60.6dB SNDR for 62.5MHz sampling frequency and 2MHz signal bandwidth. With such specification, the modulator can be applied to WCDMA wireless communication system. The power consumption is about 12.17mW at 1.2V supply. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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