A High-Performance FGS Texture Encoder Architecture Design for HDTV1080p@60FPS Application
| Autor: | Kuei-An Chen, 陳逵安 |
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| Rok vydání: | 2009 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 97 This thesis presents a high performance and low cost fine granularity scalable (FGS) texture encoder hardware architecture design which supports HDTV 1080p@60FPS real time encoding. By the desirable video scalable feature, JVT is currently standardizing a scalable extension of H.264/AVC which is also known as scalable video coding (SVC). SVC performs high video compression and supports SNR, spatial and temporal scalability. FGS method, one of the key features of SNR scalability is especially important when video transmits across channel with bandwidth fluctuation. The FGS coding bitstream can be truncated at any byte-aligned position and decoded as lower quality picture. The ARFGS scheme can improve coding performance and control drift effect at the same time. Comparing with the single motion compensation loop MPEG4 FGS, ARFGS need additional transform, leaky prediction, normalization, deblocking and motion compensation process that induce higher complexity. This work proposes a macro-block(MB)-level three-stage pipeline FGS encoding architecture which supports both key picture and non-key picture encoding. The proposed transform hardware sharing and leaky prediction hardware sharing can reduce half cost. The proposed single-port Hadamard AC SRAM can reduce 2/3 area and reduce 99% SRAM access compared with ping-pong one. In adaptive reference decision (ARD) module, the proposed non-β mode register latch technique can avoid unnecessary register shift and then reduce power consumption. In the aspect of re-quantization (REQ) loops design, we propose a new re-quantization scheme called Fast-REQ. Comparing with conventional time multiplexing REQ scheme, the proposed Fast-REQ owns 2/3 computation complexity reduction and three times throughput improvement at similar hardware cost. The Fast-REQ scheme can increase coding performance about 1 dB PSNR at low bitrate. Being implemented using TSMC 0.18μm technology, the proposed FGS texture encoder can achieve the real-time requirement of HDTV 1080p@60fps at the cost of 65k gates. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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