Optimum Design for Gold Stud Bump Thermo-compression Flip Chip Bonding Process by Applying DOE Method
| Autor: | Hui-Shan Chang, 張惠珊 |
|---|---|
| Rok vydání: | 2009 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 97 Over the years, flip chip has become the major interconnection method of high performance packages such as microprocessors, graphics chipsets, high speed memory and high-end ASICs. Flip chips apply in some high volume consumer product such as PC peripherals, mobile phones, digital cameras and MP3 players. Unlike conventional interconnection through wire bonding, flip chip uses solder or gold bumps instead. Therefore, the I/O pads can be distributed all over the surface of the chip, not only on the peripheral region. The "Gold Stud Bump Flip Chip" turns out to be the most popular flip chip technology among them. In the past two years, a key stimulus for this growth in gold stud bump flip chip applications has been the introduction a new generation of higher-speed, closer-pitch and high-density packages. And that it has the unique benefits and these benefits can be over the more common solder bump flip chips. One is reduced interconnection length and provides better conductivity and low resistivity. Another one is “Gold Stud Bump Flip Chips” offer finer spacing than most solder bumps, and it can be application to higher routing density, smaller and thinner packages. In this paper, the research is mainly with a view to develop a new process flow with low production cost for gold stud bump flip chip package. DOE (Design of experiment) methods are applied to analyze the experimental data to find the key factors of flip chip bond process. The result shows the thermo-compression flip chip bonding can be apply to gold stud bump flip chip package and the O/S test & NCP voids all can pass our spec. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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