Design and Implementation of Low Voltage CMOS Phase-Locked-Loop and Delay-Locked-Loop
| Autor: | Chung-Ting Lu, 呂宗庭 |
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| Rok vydání: | 2007 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 96 Low-power CMOS designs have attracted great attention in the past few years. For portable wireless communication systems such as mobile phones, the power dissipation of the integrated circuits is of crucial importance as it predetermines the battery life. Even for electronic products operated at household electricity, the power consumption and the associated thermal problems are still essential design issues as the packing density of a fully integrated system increases. Besides, clocks are very important in the above mentioned portable devices. Therefore, this thesis is devoted to the implementation of clock production such as phase-locked-loops and delay-locked-loops operated at low voltage with low power consumption. In chapter 3, by employing the forward-body-bias (FBB) technique and low-voltage circuit topologies for the individual building blocks, a phase-locked loop (PLL) is proposed to operate at reduced supply voltage and power consumption while maintaining the desirable circuit performance at multi-gigahertz frequencies. Using a standard 0.18-μm CMOS process, a 1.9-GHz PLL is implemented for demonstration. Consuming a dc power of 4.5 mW from a 0.5-V supply voltage, the fabricated circuit exhibits in-band and out-of-band phase noise of -83.4 dBc/Hz and -135.3 dBc/Hz at 100- kHz and 10-MHz frequency offset, respectively, and a side-band spur with a power level 44 dB below the carrier. A ring-like LC QVCO technique is proposed in chapter 4. The proposed QVCO can achieve desirable phase noise and phase error performance with much less power consumption. Push-push frequency doubler technique is also used to produce the dual band signals. This QVCO is then applied in a PLL. The forward-body-bias technique and low-voltage circuit topologies described in Chapter 2 for the individual building blocks are utilized in a phase-locked loop (PLL) at reduced supply voltage and power consumption while maintaining the desirable circuit performance at multi-gigahertz frequencies. Using a standard 0.18-μm CMOS process, a 2.4-GHz PLL is implemented for demonstration. Consuming a dc power of 12 mW from a 0.5-V supply voltage, the fabricated circuit exhibits quadrature outputs with phase noise -113.05 dBc/Hz at 1-MHz frequency offset, and a side-band spur with a power level 38 dB below the carrier. Besides, the phase error is around 0.6° and the IRR is 38dB. A low voltage, low power, low jitter, and wide range delay-locked-loop (DLL) is proposed in chapter 5. In this design low voltage circuits design approaches and the proposed voltage control delay line (VCDL) have been used to attain the above mentioned performance. Besides, problems in the conventional circuits such as linearity are solved by this new skill. In this way the delay range can cover all the control voltage. Fabricated in a standard 0.18-μm CMOS process, the simulation results show that under the supply voltage of 0.6 V, the proposed DLL can operate from 100 to 400 MHz, and the current drawn from the supply is 4 mA and 7.5 mA, separately. With the data simulated in HSPICE, the corresponding jitter simulated in the MATLAB is 25 ps to 13 ps. The DLL occupies a total area of 680 μm × 680 μm. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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