A Low Power 1-n-1 Structure FIFO implementation with GasP
| Autor: | Ming-Tse Sune, 孫銘澤 |
|---|---|
| Rok vydání: | 2008 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 96 The current trend of circuit design is towards low power, but the performance is often degraded. Therefore the circuits with power-efficiency and high performance are superior. This thesis presents a low power and high performance 1-n-1 structure FIFO implementation, based on GasP modules. In order to implement the system, we explain a method to transform the algorithm of systems into the corresponding GasP modules. Then we derived several equations to analysis the algorithm to conform our purpose before we really implement our design. Finally, we compared the proposed structure with other structures. The depths we compared are ten and eighteen, and the width is one bit. We assume that the environment sends three billion data items per second to the FIFOs and it is simulated with the TSMC 180nm process. The result indicates the 1-n-1 FIFOs almost have the best outcome. In particular, the 1-n-1 FIFO with eighteen stages has one time improvement more than the square FIFO, and the predominance is more obvious when the depth of FIFOs becomes larger. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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