Design and Implementation of the CMOS RF Front-end Circuit for WiMAX System Application
| Autor: | Chi-Feng Lin, 林琦峰 |
|---|---|
| Jazyk: | en_US |
| Rok vydání: | 2008 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 96 The purpose of the thesis is aimted at the design and implementation of LNA, differential LNA and balanced down mixer, which can be applied Worldwide Interoperability Microwave Access (WiMAX) technology of broadband to provide high data rate and transmitting data in long distance. Although the WiMAX standard (IEEE 802.16) has not been completed universally, most of the proposed applications are allowed to transmit in a band between 2 and 11 GHz (2.5 GHz, 2.8 GHz, 3.5 GHz, and 5.8 GHz etc). The proposed LNA and mixer were implemented based on TSMC standard 0.18 �慆 RF CMOS process. From the design flow, circuit simulation, layout of circuit, and measured of chip have been described completely. In first circuit, we designed a fully integrated 3.3 -3.8 GHz LNA structures, we employed the resistive shunt-feedback, LC Branch band-pass filter circuit to achieve input impedance matching. In addition, the gain stage amplifier adopts cascade structure to implement amplifier stage. The measured input return loss (S11) is less than – 10.9 dB over 3.3 – 3.8 GHz range. The maximum power gain (S21) is 19.4 dB and the minimum noise figure is 3.17 dB for 3.3 – 3.8 GHz. The 1 dB gain compression performance is approximate -24 dBm. The bias current is 7.6 mA of a 1.2 V and the power consumption is 9.12 mW. The second and third circuit, we proposed two new structures of differential LNA that can achieve good input/output impedance matching, high gain, and excellent phase error. In second circuit, due to gain and phase must be imbalanced in the conventions differential amplifier, so mismatch compensation network is generally required, therefore employ LC feedback network to compensate for this undesired effect, Although there are some differences between measured results and simulation date, after finding the reason and embed in the simulation, the circuit performance still be maintained well. In third circuit, due to power consumption and low cost must be considered carefully in receiver system, therefore we proposed the low power consumption differential phase splitters to reduce the power consumption of second circuit active baluns. The power consumption of this schematic is less 14 mW than that of the second circuit active balun, moreover saves 50% of power consumption, so this circuit can be fully integrated in RFIC for low power and low cost application. In fourth circuit, the circuit structure of the proposed mixer consists of common-gate transconductance stage, mixer cord stage and the IF buffer amplifier. In order to achieve high linear and low power consumption characteristic, we utilized the device characteristics and common-gaete topology to achieve the noise and gain matching at input port of the whole circuit. Therefore at the operation conditions of Vdd = 1.8 V, RF frequency =3.5 GHz, LO frequency =3.12 GHz, the conversion gain is about -1.45 dB, input P1dB and power consumption are about -2 dBm and 18.6 mW. The last circuit, we proposed the doubly balanced sub-harmonic mixer. We described the operating time, parameter definition and proposed a modified structure which has double frequency, source mixer and IF buffer stage. At the operation conditions of Vdd = 1.8 V, RF frequency =3.5 GHz, LO frequency = 1.56 GHz, the input P1dB and power consumption are about -8 dBm and 14.6 mW. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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