Solving Voltage Island Problem with Interconnection Delay Consideration
| Autor: | Ya-Feng Shen, 沈雅楓 |
|---|---|
| Rok vydání: | 2008 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 96 Since fabrication becomes more complex, the problem of power consumption reduction becomes an important issue. In this paper, we will explore voltage assignment problem with interconnection delay consideration because a large proportion of total delay comes from the interconnection delay in modern fabrication process. This paper has four phases: (1.) find a floorplan using Parquet [12], (2.) determine the initial voltage assignment by a dynamic programming algorithm, (3.) locally reassign the voltage of some blocks to decrease the number of voltage islands, and (4.) finally, insert level-shifters when necessary. We avoid the violation of interconnection delay after voltage assignment and keep the quality of area and wirelength of floorplanning. Experimental results show the solution by using this method can save total power which ranges form 20% to 50% without destroying the quality of floorplan. Besides, after locally voltage reassignment, the number of voltage island will be reduced. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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