Real-time De-interlace Image Processing Utilizing FPGA
| Autor: | SZU-HENG LIU, 劉思亨 |
|---|---|
| Rok vydání: | 2008 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 96 The purpose of this research was to design real-time image signal processing to achieving high quality image output. The research adopts adaptive motion compensated de-interlacing algorithm to process interlaced scanning image signal, real-time output progressive scanning image signal of high dpi in LCD monitor. The use of the de-interlacing algorithm adopted in the system, affects the quality of the output image. The complexity and simplcity of the algorithm affected the area and the attrition energy of the chip. This paper adopts adaptive motion compensated de-interlacing algorithm. Using of verilog HDL, to write for the register transfer level, and then burn to DE2 program on the FPGA(Field Programmable Gate Array) that to verify the feasibility of the theory, If use the software operation, it will certainly not be achieved the needs of real-time process. As the research deals only with the use of algorithms in the brightness signal Y.It needs CPU of operation cycle above 5 GHz. So use of hardware FPGA accelerated image processing. Therefore, also do not to send the chip layout making the actual IC, to complete the verification steps. The system designed in the research, mainly based on four parts: motion detection, spatial-interpolation, temporal-interpolation, median filter. Under the NTSC format, increase in output per second for 60 screen. Output images and Matlab simulation of the other five commonly used algorithms comparison. The results of the MSE value of the minimum and maximum value PSNR. Show that the research has reached to high-quality images output. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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