A Multi-Core SOC Design in Virtual Integration Platform and FPGA
| Autor: | Tsung-Yi Chou, 周宗頤 |
|---|---|
| Rok vydání: | 2008 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 96 Now multi-core SOC is a predictable trend to increase the system performance, but the complexity of multi-core design is very high. For this reason, it is getting much harder of verification in RTL / gate level. So we construct a fast and accurate VIP (Virtual Integration Platform) for system development and verification purposes, so that the entire system can be verified earlier in software stage at the system level, instead of waiting until RTL is finished. CUBA is a virtual bus that we designed for simulating AMBA 2.0 AHB. Now we implement three different types of simulation accuracy, trading different simulation speed for accuracy. We integrate CUBA and existing CPU ISS into a virtual platform of multi-core. The platform provides software development at an early stage for software developers, and also provides evaluation of hardware design for hardware designers. We propose a technology, called Virtual I/O that can access the resources of real board directly on the virtual platform. By using the technique of Virtual I/O, we can directly control the devices of real development board on the virtual platform without designing other SystemC or C IP models in VIP, such that we can reduce the development time. Because of using the devices of real board directly on the virtual platform, we can enhance the reliability of verification. We not only implement multi-core system on VIP, but also on the FPGA. In the experiment, it shows our VIP provides fast and accurate simulation. Now we have ported SPLASH-2 on octa-core in VIP and executed successful. We also construct the quad-core in FPGA and execute JPEG decoder on it. With this software simulation to hardware emulation design flow, we can easily map VIP to FPGA and reduce development time. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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