Design of Energy Efficient Successive-Approximation Analog-to-Digital Converter
| Autor: | Guan-Ying Huang, 黃冠穎 |
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| Rok vydání: | 2007 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 95 In this thesis, two successive-approximation (SAR) analog-to-digital converters (ADCs) are proposed. In the first ADC, a novel RC time constant capacitor array, which adjusts the numbers of switch, is used to speed up the conversion rate. And a self timing controller is used to control the comparator, which can save half of the power consumption of the comparator. Simulation results of the first ADC, an 8-bit 27 MS/s SAR ADC, show that the total power consumption is 385 μW and the average energy consumption per conversion step is 105 fJ in the TSMC 0.13 μm process. In order to further increase the conversion rate, a novel capacitor array with passive charge-sharing (PCS) technique, which can effectively reduce the total power consumption and the input capacitance, is used in the second ADC. Simulation results of the second ADC, an 8-bit 50 MS/s PCS SAR ADC, show that the total power consumption is 294 μW and the average energy consumption per conversion step is 41 fJ in the TSMC 0.13 μm process. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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