A Less Memory and Less Bit Requirement Architecture for the Discrete Wavelet Transform
| Autor: | Guan-Nan Chen, 陳冠男 |
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| Rok vydání: | 2007 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 95 Discrete Wavelete Transform(DWT) is an efficient technology of analyzing signal and is the kernel technology of JPEG2000 as well. In this thesis, we propose a new methodology of rearranging Flipping-based DWT to get a low-cost and high-performance 2D DWT architecture. The proposed architecture consists of three main components which includes the column processor, the transposing buffers and the row processor. The column processor contains four multipliers, eight adders, sixteen registers and 4N temporal memory. The transposing buffer is used to replace original memory. Similarly, the row processor contains four multipliers, eight adders and twenty-four registers. There exist less register requirement to replace temporal memory because row processor applies row-wise scanning method. In this thesis, we also discuss the relation between data bit width of proposed architecture and PSNR of input picture. Here, we can maintain the qualified PSNR with less width of data bit while comparing with others. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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