Efficient BIST Techniques for Wavefront Array Processor for Motion Estimation and Compensation in the Transform Domain
| Autor: | Wei-Yang Liu, 劉為元 |
|---|---|
| Rok vydání: | 2007 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 95 Testable design techniques for a systolic motion estimator based on C-testability and M-testablility conditions are proposed in this paper. The systolic array in motion estimator can be viewed as a two-dimensional iterative logic array (ILA) which is composed of processing elements (PE) and multiplication element (MUL). The function of each multiplication element is modified to be bijective to meet the C-testable and M-testable conditions. The number of test patterns in module level is 2w, where w denotes the wordlength of a multiplier. In order to reduce testing time, the DFT technique which is proposed in [20] is used in bit level. The faults in Booth Multiplier [20] are not only detected but also corrected in this paper. The test patterns are transmitted as a 45° tessellation. The BIST in module level and bit level can achieve 99% fault coverage. In our design, faults are not only detected but also located. The total area overheads are acceptable-about 6% and 4%, respectively. To verify our approaches, an experimental chip is implemented. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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