Design of A 32-bit Multi-Function LNS Arithmetic Unit on An SOPC System And Its Applications
| Autor: | Min-Nam Yen, 顏敏男 |
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| Rok vydání: | 2007 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 95 Arithmetic units used for performing basic operations, especially for microprocessors and digital signal processors, are the most important components in the digital systems. When arithmetic units are designed, their architecture, precision, area of circuit, delay, and power consumption of the circuit will usually be affected by different number systems selected. My thesis compared and analyzed the Floating-Point (FLP) Number System, and Logarithmic Number Systems (LNS) based on the design of a 32-bit arithmetic unit. We proposed a new architecture in the addition and subtraction of LNS. As long as we can take control of the signal line under this architecture, we can easily get six different kinds of complicated functions,,, and by using the same hardware circuit, and achieve the objectives of sharing hardware and reducing the payable cost. We implemented the arithmetic units of FLP and LNS by using hardware description language. After simulation and verification by ModelSim, we integrated FLP and LNS into the development environment of Nios SOPC system by utilizing custom instructions so that they can be called by application software. We designed three simple application instances (Kinetic Energy, Potential Function, and Sine Function) carried out via FLP and LNS to get the comparative analyses of the FLP and LNS in terms of their execution efficiency and hardware cost. Finally, we can infer some benefits and drawbacks of the FLP and LNS and when we can use them in the arithmetic system, according to the results of the comparative data. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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