Design of CMOS Frequency Synthesizer for Electromagnetic Micro-Motion Detection System
| Autor: | Yung-Chung Chang, 張永忠 |
|---|---|
| Rok vydání: | 2007 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 95 Two CMOS VCOs and two CMOS frequency synthesizers for electromagnetic micro-motion detection system are proposed in this thesis. They include low-phase-noise quadrature VCO with harmonic resonating network, low-phase-noise VCO with self-cascoded coupling, fast locking integral-N frequency synthesizer, and sigma-delta fractional-N frequency synthesizer, respectively. On the low-phase-noise quadrature VCO with harmonic resonating network, the harmonic resonance and cascode coupling methods are used for phase-noise reduction. The measurement results show that a phase noise of -125.3 dBc/Hz at 1-MHz offset at 915 MHz, what the output frequency is from 823 to 948 MHz, and output power larger than -2.8 dBm. On low-phase-noise VCO with self-cascoded coupling, the measurement results show that a phase noise of -123.6 dBc/Hz at 1-MHz offset at 915 MHz, what the output frequency is from 828 to 990 MHz, and output power larger than -1.9 dBm. On fast locking integral-N frequency synthesizer, its settling time and phase noise are reduced by the adoption of nonlinear PFD and harmonic resonated VCO. On sigma-delta fractional-N frequency synthesizer, the phase-noise reduction is accomplished by the techniques of feedback-controlled charge pump, self-cascoded coupling VCO, and sigma-delta fractional-N divider. The measurement results show that the frequency locking range is from 4 to 4.7 GHz, the settling time is 150 us, and the phase noise is -54.7 dBc/Hz at 10-Hz offset at 4.4 GHz. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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