A Monolithic Vernier-Based Time-to-Digital Converter with Dual PLLs for Self-Calibration
| Autor: | Jia-Chi Zheng, 鄭家麒 |
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| Rok vydání: | 2005 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 93 A monolithic Vernier-based time-to-digital converter (TDC) with 37.5ps time resolution and theoretically unlimited input range has been integrated in 0.35-m standard 2P4M CMOS technology. A single-stage Vernier delay line is used for both coarse and fine measurement without the need of any other interpolation circuit. The operation frequencies of Vernier delay line are stabilized against process variations and ambient conditions by a novel dual phase-locked loops circuit. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration problems. The measured differential nonlinearity is 0.2LSB, and the measured integral nonlinearity after averaging 500 samples is 0.7LSB. The power consumption is 150mW, and the chip size is as small as 0.222mm2. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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