Design and Analysis of a 20-GHz Clock MultiplicationUnit in 0.18-um CMOS Technology
| Autor: | Sheng-Hann Wu, 吳昇翰 |
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| Rok vydání: | 2006 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 94 A 20-GHz clock multiplication unit for SONET OC-768 systems employs dual loops and third-order loop filter to suppress the jitter. Realized in 0.18-um CMOS technology, this circuit achieves an output jitter of 0.2 ps,rms and 4.5 ps,pp while consuming 40 mW from a 1.8-V supply. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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