ANALYTICAL PROGRAMMING MODEL AND APPLICATIONS OF SPLIT GATE FLASH MEMORY
| Autor: | Yu-Hsiung Wang, 王馭熊 |
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| Rok vydání: | 2005 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 94 In this work, we present a comprehensive and accurate analytical model for evaluating the full transient programming behaviors of the drain-coupling split gate flash with dynamic drain coupling ratio for the first time either on the constant pulse for binary storages or on the staircase pulse for multilevel applications. Starting with the quasi-2D analysis on the bias-dependent and time-varying drain coupling ratio, our programming model based on the constant barrier height approximation and Lucky-Electron Model (LEM) is developed to simulate the complete operation plot of the time to program versus the programming voltage with various programming targets and technology parameters. The intrinsic coupling ratio independent of the storage charge is presented as the key figure of merit for the design index of the device. Besides, the analytical predictions of the variance of the read current distribution for binary and multilevel memory array are also presented. The extracted re-direction mean free path of our Source-Side Injection (SSI) device is smaller than that of Channel Hot-Electron (CHE) device by one order of magnitude provides the physical intuition of the derived high injection efficiency around 2/1000 for our SSI device. The feasibility for the multilevel SSI drain-coupling flash is theoretically and experimentally demonstrated. The design guidelines of program speed and program accuracy for multilevel programming are brought out by our analytical programming model. The mechanisms of cycling window closure are also discussed and new ramped-programming pulse method is proposed to improve the endurance performance significantly. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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