Study of Nano-scale Copper Metallization on Damascene Process Integration for Semiconductor Integrated Circuits

Autor: Kei-Wei Chen, 陳科維
Rok vydání: 2006
Druh dokumentu: 學位論文 ; thesis
Popis: 94
With semiconductor manufacture shrunk down to the 100 nm technology, the interconnection of the device would be faced to the nano-scale manufacturing and integration. The nano-scale interconnection could reduce the high power consumption and heat accumulation, even shrink the chip volume and device sizes. The nano-scale technology and manufacture for interconnection would be induced with the copper and low-K dielectric materials, instead of the original aluminum and silicon oxide materials. Copper manufacturing technology has been developed with damascene process. It would be the key method for the copper metallization, due to the copper etching suffered with the low vaporization capability and its high chemical activity. The process would be changed from the original metal pattern defined first then dielectric oxide deposition to the dielectric oxide etching then copper metal deposition. This change involved three major key process introductions, such as the barrier and copper seeding deposition, copper electrodeposition (ECD), and copper chemical mechanical planarization (CMP) processes. Especially for the nano-scale manufacturing, the processes would be challenged with the process integration, precise interconnection alignment in lithography, process defect management issues and so on. This thesis would be focused on the copper interconnection manufacturing issues and skills for the requirements of the nano-scale interconnect. Besides, we will not focus on the low-K material introduction and integration in the damascene process, due to this big topic and subject being separated into the other discussion and theme. From the view of the nano-scale interconnection manufacture, the barrier and seeding deposition would be changed from the original convectional physical vapor deposition (PVD) methodology to the combination technology of the sputter and resputter processes or the chemical vapor deposition (CVD) methodology for copper metallization. In this thesis, we will discuss these technology and process for the nano-scale issues. Besides, the copper electrodeposition is another key process for the nano-scale interconnection. It is necessary for the nano-scale plating to achieve the super-filling in the damascene features without any defects and voids in the interconnection. Hence, the process would be mainly discussed with the overpotenital effect from the thinner seeding layer and controlled with the copper grain size distributions. Theses discussions and integration will be described in the chapter 5. Furthermore, the copper CMP process is the most key and difficult process in the copper metallization, due to its immature process integration and manufacture. Besides, the copper CMP needs to be challenged with the dishing effect and the precise process control of the polishing removal rate. Then, we introduce and develop a novel slurry with the passivation concept to overcome the difficulties of the nano-scale planarization. This passivation type of the slurry is composed of the long-chain carbon structure to act as a buffer between the abrasives and the unsmooth topology of the copper. In chapter 6, we also discuss the phenomena of non-linear or non-Preston’s polishing behavior from this slurry and understand its mechanism through simulation. The polishing kinetics and simulation on commercial polishing platforms had been studied in this chapter to reduce the defect and resolve the process control issue. Finally, we discuss the issues of the process integration and reliability in chapters 7 and 8. The integration and reliability issue would be focused on the pattern density effect on the process manufacture and its reliability problem. We present the mechanism and the solution of these issues for further improvement of the manufacture qualities.
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