Design of 10-Bit 500MSample/s Current-Steering Binary-Weighted DAC
| Autor: | Jian-Ming Fu, 傅健銘 |
|---|---|
| Rok vydání: | 2006 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 94 Digital to analog converter (DAC) is widely used in many modern audio and communication system. Such as: digital TV, and radio transmitter etc.. For the applications, a high speed DAC with suitable resolution is required. In the thesis, a 10-Bit 500MSample/s Current-Steering Binary-Weighted DAC is presented. In order to achieve high linearity and spurious free dynamic range (SFDR), four technique is adopted, including of using binary-weight coding to reduce the circuit area, current source arranging in current source array (CSA) to decrease process variation, using randomization to average non-linearity error, and employing a deglitch latch to improve dynamic performance. For a 500MHz sampling rate, the SPDR of 69dB at 100MHz signal frequency is achieved. The converter consumes total 90 mW. The chip is implemented in a standard TSMC 0.18-mm 1P6M CMOS technology. The converter active area is 0.6 mm2. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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