Design of Pulsewidth Control Loop with a Built-In Delay-Lock Loop
| Autor: | Wen-Wei Zhou, 周文偉 |
|---|---|
| Rok vydání: | 2006 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 94 In system chip, PLL and DLL are mostly used to generate the clock for different sub-circuits in the system. Therefore, the quality of clock signals will influence the efficiency of the entire system. This thesis introduces a pulsewidth control loop with a built-in delay-lock loop circuit, which has two main function: duty cycle presetting and phase lock. To make the duty cycles more accurate, a two-step duty cycle presetting scheme is proposed; the first step selects the region of duty cycle digitally, and the second step uses an analog signal to fine tune the duty cycle. The circuit is designed by using TSMC 0.18-μm 1P6M COMS process. The presetting range of duty cycle of generated clock is from 26.65% to 68.03% when operating at 1.25GHz and 1.8V power supply. Its power consumption is 43mW. The core size is 468μm×147μm. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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