Hardware Design of an Adaptive Neuro-Fuzzy Network with On-Chip Learning Capability and Fine Grain Pipeline Structure
| Autor: | Chun-Chang Yu, 余俊璋 |
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| Rok vydání: | 2006 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 94 This thesis focuses on a digital hardware implementation of an adaptive neuro-fuzzy network with on-chip learning capability. We adopt a backpropagation learning algorithm to optimize the network parameters. To minimize the computational time and resources, we proposed to share the computational results in both feedforward and backpropagation paths. That is, the results of data computation required in the feedforward path are stored in buffers to establish a database that enables the backpropagation circuit to retrieve the necessary data when calculating the error gradients. This improvement leads to a simpler data flow and the reduction of resource consumption. Then we adopt an integer linear programming to obtain an optimal schedule. After the data path analysis, we divide feedforward path into three asynchronous parts to reduce power consumption and prevent the problem of clock skew. Each part is realized by a synchronous fine-grain pipeline architecture to get high computational speed. The backpropagation learning path, however, is simply a synchronous pipeline architecture because of the continuous update process and resource limitation. In addition, we follow the guidelines of silicon intellectual property so that our circuit can become a reusable, flexible, and configurable module for system integration. To verify the circuit, we implement the circuit in a FPGA develop board and validate the effectiveness in an intelligent car-driving system. The simulation results have shown that our circuit performs well in speed, accuracy, and resource sharing. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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