CMOS Frequency Synthesizer Design for IEEE 802.11a WLAN Applications
| Autor: | Jia Hau Liang, 梁嘉豪 |
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| Rok vydání: | 2004 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 92 The communication product is continually decreasing in price, the function diverse, light weighted, and thanks to high frequency band and small volume, electric consumption has been reduced symbolizing the great strides of the fast growing wireless communication industry. Through the product miniaturization being the chip, accumulation in the body and high frequency has become an inevitable tendency. The phase lock loop in integrated circuit in each kind of domain apply quite widely. An example of this is that the frequency producer of communication frame, signal demodulation system and the synthesizer of wireless communication system all has the phase lock loop the trace. This paper’s purpose is to study and design the frequency synthesizer so that it can be applied to IEEE 802.11a WLAN 5GHz U-NII and have it fall in the frequency receiver system. In addition, the design should conform to IEEE 802.11a WLAN being the standard system request. The frequency synthesizer is realized in TSMC 0.18 µm CMOS one-poly six-metal (1p6m) process which runs off of a 1.8 volt supply, and first adopt the Altera MAX+plus II software in the design of confirmation, then finally uses Agilent ADS (Advanced Design System) which is the software that achieves CMOS. The circuit design may divide into low frequency and high-frequency unit with the low frequency partially containing phase frequency detecting, the charge pump and the loop filter. It has the fast cut speed and the resistance noise has a better positive feedback CMOS structure for charge pump design. Considering the loop filter aspect to the phase-lock loop of loop width, the phase noise, the loop filter design outside the chip, and the affiliation achieved by the adjustment loop filter element value has the best return route loop width and the phase noise. The high frequency partial design has the frequency divider of dual-modulus prescaler and voltage control oscillator. Then the frequency divider aspect uses pulse-swallow counter structure. In addition, we adopt TSPC (True Single Phase Clock) topology with high speed dynamic D-type flip flops to complete the integer-M frequency divider circuit. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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