Low-Power Design and Implement of the Multi-MPEG Motion Compensation IP Core
| Autor: | Lin-Chieh Huang, 黃麟傑 |
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| Rok vydání: | 2004 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 92 Motion compensation is one of the core techniques for video compression in many multimedia applications. This technique is taken by several well-known video compression standards, such as MPEG-1, MPEG-2, MPEG-4, and H.26x. Motion compensation is popularly used for reducing the temporal redundancy to enhance the compression ratio. Owing to the huge computations performed by fractional-pixel interpolation, the processing time and power consumption of motion compensation become one of the major computing parts for a video decoder system. For high image quality requirements (such as HDTV) and low-power requirements in portable application in mobile devices, a high performance and low power consumption motion compensation design is more and more demanding for current video decoder systems. This thesis concentrates on low-power Motion Compensation (MC) design for the Multi-MPEG (MPEG-1/2/4) video decoder. The proposed design approaches include a FIFO-based MV predictor, an Adder-based interpolator for low cost consideration, and a Dynamic Partial Guarded Computation Interpolator (DPGCI) technique that divides the operation into needed-compute part and unneeded-compute part and freeze the unneeded-compute part to achieve the low-power dissipation target. This thesis not only presents the MC IP core design, but also discusses MC design on processors to accelerate the MC operation of video decoding on general proposed processors. To ensure the validity of the proposed MC design, we verify the proposed design in several different levels such as Behavior functional verification, RTL verification, gate level verification, and FPGA verification. Besides, we use Synopsys Formality tool to compare the equivalence between RTL and gate level. The proposed design uses UMC 0.18 µm CMOS technology. In addition, the power consumption of interpolation operation in the proposed design is reduced from 60.3538 µW to 18.3863 µW when operating at 54 MHz under 1.8V supply voltage. The saving power-consumption is more than 60% by using NANOSIM measurement on the netlist level. To keep the quality of the proposed design, it has been qualified through RTL coding check by NOVAS nLint and coverage check by ModelSim Code Coverage tool in terms of 100% code coverage. Finally, the proposed design has been integrated into a MPEG-4 video decoder IP that has been verified in the Xilinx multimedia board. The FPGA prototyping could achieve the MPEG-4 CIF video real-time decoding when operated at 27 MHz. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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