Analysis and Design of Low-Power CMOS Direct Digital Frequency Synthesizers

Autor: Shiang-Jiun Lin, 林香君
Rok vydání: 2003
Druh dokumentu: 學位論文 ; thesis
Popis: 91
Owing to the fine tuning and fast frequency switching of Direct Digital Frequency Synthesizers (DDFS), it is very suitable for the strict requirement with the frequency, like communication system and instrument. Especially in recent years, the popularized of the wireless applications and portable devices, low power issues become the major trend in VLSI design. In this thesis, the previous works of DDFS were surveyed and realized that importance of in lowing power in DDFS. Furthermore, the previous works were redesigned carefully and found that the Taylor-series-based linear interpolation scheme based on Taylor series can have benefits of lower power consumption. Moreover, because of employ the digital design flow, the scheme has all of the advantages in the digital design, like insensitive of process and temperature variations, high noise margin, high immunity of supply noise and variation, short design term, and easily redesign for new specifications, and etc. From the conventional architecture, this thesis proposed five new technologies to im-prove the speed and power consumption. First, replace the compiler-ROM with the synthesized-ROM. Second, choose the proper circuit parameters. Third, employ the low-error fixed-width sign-magnitude multiplier. Fourth, adopt the carry select adder. Finally, pipelined. Using the above five techniques, in 0.35m process, comparing with the best conventional circuit, the new design can improve 40% of speed or save 88.5% of power consumption. Finally, a chip of100db SFDB, 300MHz, 32bit quadrature DDFS with the proposed new techniques was designed and implemented in 0.25m process, by Artison cell li-brary. When the chip worked in 2.5V, the power consumption and area are only 89mW and 1.8*1.8mm², respectively.
Databáze: Networked Digital Library of Theses & Dissertations
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