A congestion-Driven Multilayer Global Router with Cross Point Assignment
| Autor: | Chiao-Yi Huang, 黃喬逸 |
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| Rok vydání: | 2002 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 90 As VLSI process technologies evolve into the deep sub-micron era, the number of cells, pins, and nets in a fixed chip area becomes larger. VLSI routing is much more difficult than ever before. Traditionally, global routing is performed with a total disregard of the positions of pins and their relative topological relation, as well as the existence of electrically equivalent pins. In this thesis, we implement a congestion-driven global router with cross point assignment (CPA) to address the above issues. The research work has to developed a pin relation graph to represent the relative topology of pins in each global routing grid (GRC), an approach to dividing multi-terminal nets into a set of two-pin nets, an algorithm to find a least congestion and shortest route for each two-pin net, and a method to perform CPA for each GRC. For each net, we generate a tentative route which is improved further to reduce local congestion by exploring equivalent pins based on pin relation graphs. Some MCNC benchmark circuits are used to evaluate the effectiveness of the proposed method. The estimated wire length of a design routed by our router is about 35% shorter than that obtained by Cadence Silicon Ensemble. However, our router results in about 45% failed connections when there are only two routing layers. Future work is proposed to make our global router more robustable. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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