Design of a Hierarchical Production Scheduling Environment for Semiconductor Fabrication
| Autor: | Ting-Kai Hwang, 黃亭凱 |
|---|---|
| Rok vydání: | 2002 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 90 This dissertation describes the design of a two-level hierarchical production scheduling engine for semiconductor wafer fabrication factories (fabs). It includes a mid-term scheduler and a short-term scheduler. The mid-term scheduler considers maximizing the production flow in order to reduce the fab-wide cycle time and ensure on-time delivery to meet business goals. It respects fabrication constraints such as flow balance, machine capacity, penetration limitation of production flow and the necessity of meeting output demand to properly set daily production target volumes and reference wafer-in-process (WIP) levels for individual part types and stages. To bridge the gap between the fab-wide and the local activities, the mid-term scheduling result is then broken down into more detailed schedules by the short-term scheduler. The short-term scheduler refers to the managerial resolution for shop-floor operations and coordinates with the overall objectives of the mid-term scheduling by maximizing the production flow while tracking the daily production targets and the reference WIP levels specified by mid-term scheduling results. To be capable of providing quick answers to “what-if” analysis, the effective optimization-based Lagrangian relaxation approach is applied to both schedulers. Test results using field data indicate that the two-level scheduling tool can improve throughput and reduce variations in output. By exploiting the scheduling results, a variability analyzer and a fast rescheduling what-if analysis tool are also developed to assist evaluation of the decision options for production planning. This dissertation further analyzes another scheme for mid-term level scheduling, which focuses on industrial practice of daily production target setting and has been successfully applied to real fabs. Because of the reentrant feature in semiconductor fabrication, (i.e., a product may visit a machine group more than once in various stages of its production sequence) how the capacity of each machine group should be allocated to various stages requiring the machine group to achieve production objectives poses a unique and challenging problem of production control. For this problem, Chang et al. 1992 designed a solution scheme based on the concepts of fixed-point iteration and proportional control, which iteratively allocates machine capacity to individual stages proportional to the workloads of these stages (IPCA). Field implementations of the IPCA scheme have successfully achieved volume targets while reducing WIP and cycle times and balancing the production over the line. Due to the importance and the successful field application results, the IPCA scheme is mathematically formalized and its properties are analyzed in this dissertation. The fixed-point iteration problem is first transformed into a nonlinear polynomial root finding problem. By mathematical induction and showing the equivalent optimization problem of the nonlinear polynomial root finding problem as a strictly convex programming problem, it is proven that there exists a unique fixed point of IPCA scheme for any initial WIP distribution. Furthermore, it is shown that a reentrant line will reach a balanced equilibrium state under a repetitive application of the IPCA scheme over time. This proof adopts a weighted square deviation of WIP distribution from the equilibrium as a Lyapunov function and applies the theory of majorization to show the convergence to a balanced equilibrium. These analyses of the IPCA scheme also yield insights of continuous improvement and asymptotic stability in operating a reentrant production line. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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