ryptography chip with random number generator embedded
| Autor: | Li-Qun Huang, 黃立群 |
|---|---|
| Rok vydání: | 2002 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 90 As wireless LAN and E-commerce becomes popular today, mobile computing and communication device market is poised to overtake the desktop computing market. The widespread adoption of Internet combined with the “anytime anywhere” access of mobile devices is driving a huge growth in mobile e-commerce applications. We should encrypt and decrypt the sensitive data to protect these data effective. The WEP algorithm is essentially the RC4 cryptographic algorithm from RSA Data Security. To date, there are many papers proposing the weaknesses within RC4, the underlying encryption mechanism used by WEP. We were able to recover the 128 bit secret key used in a wireless network, with a passive attack. We conclude that 802.11 WEP is totally insecure, so we will design a more secure cryptography system in this paper. Today, two cryptosystems are used; one is the symmetric-key cryptosystem, for example, DES (Data Encryption Standard), and another is the public-key cryptosystem, for example RSA (Rivest-Shamir-Adleman). DES cryptosystem are usually used in encrypts and decrypt of the main body, and RSA cryptosystem are used in data authentication. DES, the Data Encryption Standard, can no longer be considered secure because its 56-bit key is too short. We must have a better cryptography system to instead of DES so The Rijndael algorithm was designed by Dr. Joan Daemen and Dr. Vincent Rijmen. AES supports keys of at least 128 bits and the embedded random number generator can prevent the key from being stolen. In this thesis, we use iteration architecture to design AES modules. Moreover, consider with the feature of the algorithm of encrypt and decrypt are symmetric, we combine these two circuit and using latches instead of registers to reduce the total area. By using analog circuits to make a random generator we can get true random numbers which are aperiodic, unpredictable and statistically random. We use TSMC 0.35 um process with Avanti high performance cell library to implement our chip. The layout area is 2970 x 2970 um2. The maximum clock rate can reach 65 MHz, and average power consumption is 213 mW. The result can be contribution to wireless LAN and E-commerce application. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|