On-line Real-time Fault-Tolerant VLIW Processor
| Autor: | HSUEH CHUNG LIU, 劉學忠 |
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| Rok vydání: | 2002 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 90 Recently, VLIW processor attracts much attention in that it offers high instruction level parallelism and reduces the hardware design complexity. VLIW processor has a fine-grain parallel structure, so it is feasible to incorporate the fault-tolerant design into the VLIW processor to raise its operational reliability. The problem is how to achieve the fault tolerance and enhance the system reliability, but not to increase much of the system design complexity、hardware overhead、compiler complexity and performance degradation. First of all, we propose a comprehensive fault-tolerant framework for VLIW processors, which consists of the fault diagnosis and recovery. One thing should be emphasized that the faults conquered are not only the permanent faults but also the transient faults. The recovery used here is to tolerate the transient faults. Then, we implement the proposed design of fault-tolerant VLIW processor in VHDL. The approaches of fault injection into VHDL models and fault simulation are used to validate and analyze the proposed fault-tolerant VLIW processors. The environment of fault simulation is built by developing a fault injection tool for automatic fault injection into VHDL models at chip-level, register-level and gate-level during the fault simulation. The special simulator commands of VHDL will be employed to achieve the fault injection. The data analysis w provides the experimental results that indicate, for example, the error-detection coverage, error-detection latency, performance impact and reliability etc. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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