Timing Optimization for Dynamic PLAs
| Autor: | Ya-Yun Liu, 劉雅芸 |
|---|---|
| Rok vydání: | 2002 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 90 Dynamic PLA has become popular in designing high performance microprocessors because of its high speed and predictable routing delay. Most previous researches on PLAs were focused on area optimization. However, in high performance circuit designs, timing is more critical than the area consideration. Traditionally, buffer/transistor sizing techniques are applied for the timing optimizations of dynamic PLAs. However, those techniques can only have limited improvement if the size of dynamic PLAs or the loading of its critical path is too large. In this thesis, we present three different techniques to optimize the timing of dynamic PLAs, including output phase assignment, Shannon expansion and Roth Karp decomposition. Each of these techniques not only can improve the speed but also has a regular structure of layout. The regularity of a PLA layout allows us to write efficient PLA compiler to automatically generate the layout from a set of Boolean equations. We have performed experiments on a large set of MCNC benchmarks as well as real industrial cases and the results are very exciting. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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