A Compiled-Code Simulation Technique for RTL Designs
| Autor: | Kai-hui Chang, 張凱揮 |
|---|---|
| Rok vydání: | 2001 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 89 As the technology of VLSI improves, logic simulation is getting more and more important, and various techniques that increase the speed of simulation are developed. One of them is compiled-code technique. Previous works by Lewis or Maurer focused on gate-level designs. Because RTL simulation is getting important now, we proposed an approach that can accelerate the simulation of RTL designs as well as gate-level designs. There are some compiled-code simulators available commercially like NC-Verilog from Cadence and VCS from Synopsys. Their approach is to write a new simulator which generates machine code directly. The advantage is that the performance can be optimized to a maximal. The disadvantage is that it takes a very long time to develop a totally new simulator, and takes more effort to maintain two different simulators. We took a different approach on the use of compiled-code techniques. From some analysis, it is found that the most time consuming part in simulation is not on the scheduler. It is on the evaluations of expressions. Thus we decided to keep the interpretive scheduler and write out design-specific evaluations to C code. It takes much less effort than writing a totally new simulator, while exploiting the advantage of compiled-code techniques. The improvement in performance is significant, though not comparable with commercial products yet. In the future, if machine code is generated directly, the performance will get close to commercial products. The experimental results show that the simulation time can be shortened between 25% to 79%, depending on the design. For circuits with more complex evaluations, the acceleration could be more significant. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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