A timing-driven force-directed floorplanner
| Autor: | Chou Hsiang Yu, 周相攸 |
|---|---|
| Rok vydání: | 2001 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 89 We propose a timing-driven non-slicing floorplanner based on a modified force-directed method in this study. In deep sub-micron design, timing closure issue becomes more critical than chip area. We extract critical paths from gate-level design to and formulate the timing information as the attractive force between blocks and I/O pads. To obtain a feasible solution, a 3-phase approach is employed. The proposed approach can solve timing closure issue in early physical design phase and produce a feasible floorplanning result. We perform experiments on real cases circuits. Experimental results indicate that our floorplanner reduces wire length and performs well in the test cases. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|