ESD implantations and new diode structures in sub-quarter-micron bulk CMOS technology
| Autor: | Che-Hao Chuang, 莊哲豪 |
|---|---|
| Rok vydání: | 2001 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 89 In this thesis, the influence on ESD robustness with the different ESD implantations and layout design on gate-grounded NMOS (GGNMOS) and gate-VDD PMOS are investigated in a 0.18-µm salicided CMOS technology. A novel diode structure to avoid the formation of the LOCOS (local oxidation of silicon) field oxide isolation between the p/n junction of diode in the CMOS process has been fabricated in a 0.35-µm polycided CMOS technology. In the first part, the methods to sustain the higher ESD level in a 0.18-µm salicided CMOS technology are discussed. A method to enhance the ESD robustness of the protection device is through the process design. The second breakdown current (It2) of the NMOS devices with different ESD-implantation solutions for on-chip ESD protection are measured by the transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. The significant improvement is observed when the NMOS is fabricated with both boron ESD implantation and arsenic ESD implantation. Except the ESD implantations method, the layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness in a 0.18-µm salicided CMOS process is also investigated. The multi- finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but still to provide deep- submicron CMOS IC’s with higher ESD robustness. In the second part, a novel diode structure to enhance the ESD robustness is discussed. A PMOS is especially inserted into the diode structure to form the PMOS-bounded diode, which is used to block the field oxide across the p/n junction in the diode. An NMOS is especially inserted into the diode structure to form the NMOS-bounded diode, which is also used to block the field oxide across the p/n junction in the diode. Without the field oxide boundary across the p/n junction of diode structure, the proposed PMOS-bounded diode and NMOS-bounded diode can sustain a much higher ESD stress, especially under the reverse-biased condition. Such PMOS-bounded diode and NMOS-bounded diode are fully process-compatible to the CMOS process without additional process modification or mask layers. Such new diodes have been successfully verified in a 0.35-µm LOCOS CMOS process. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|