CMOS RF Front-End Circuit Design for DECT System Application
| Autor: | LIN, CHEN-CHING, 林陳慶 |
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| Rok vydání: | 2000 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 88 Wireless generation is prompted by the inconvenient of wired. Portable personal communication systems such as cellular phones, cordless phones, PDA and pagers, has become a part of our daily lives. Low cost, low power, high level integration and minimizing external components are the objects designers seek recently since rapid development in semiconductor integrated circuit and portable communications market. However, they are built in mixture of IC technologies traditionally. Baseband DSP circuits could build from CMOS technology. However, the analog front-end which has to operate at radio frequencies are traditionally built from more expensive technologies like GaAs or silicon bipolar which are optimized to provide signal amplification at radio frequencies. CMOS technology continuous improvement as its scales with low cost are making silicon an increasingly attractive technology for microwave wireless communication circuits. It becomes possible to integrate complete communication system on a single chip including RF and baseband circuits using low-cost CMOS technology for fit the common requirements of low-cost, low power and small size. This thesis introduces a highly integrated 1.89GHz CMOS RF front-end receiver for Digital Enhanced Cordless Telecommunications system implemented by using the TSMC 0.6μm SPTM standard CMOS technology. Intermediate frequency is set to 240 MHz for image reject ratio requirement. It composed of a single-ended low noise amplifier, image reject mixer, local oscillator input buffer, and IF down-conversion quadrature generator. Image-reject architecture eliminates off-chip SAW filters often seen in heterodyne receivers. In order to boost the gain performance and achieve low voltage design, planar inductors are used in LNA and on-chip bias Tee is used for testing consideration. For high-Q filtering, active inductor is used in summing circuit. A single chip image-reject RF front-end receiver for use 1.9GHz band has been implemented in a 0.6μm CMOS technology. It has 43.9 dB cascaded voltage gain, 2.28dB noise figure in LNA, -71.4dB image rejection ratio, and -20.2dbm input intercept point referred to the LNA input. Total power consumption is about 119mW at 2.5V supply voltage. The chip size is about 2300 μm by 2300 μm. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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