Parallel Logic Simulation for VLSI Verfication
| Autor: | Rung-Ji Shang, 尚榮基 |
|---|---|
| Rok vydání: | 2000 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 88 As the complexity of digital design continuously increasing, logic simulation becomes a crucial verification task in VLSI design. Traditional parallel logic simulation suffers from synchronization constraint and high data transmission rate. In this thesis, we will propose a new technique of parallel logic simulation that running on distributed environment. The logic simulation combines both the advantages of event driven simulation and cycle based simulation. We use the cycle based simulation to fast generate the synchronization information, and use the event-driven simulation to report the accurate timing results. Both the cycle based simulation and event driven simulation can be partitioned and distributed on time domain and space domain. Based on different partition strategies, we will propose four different parallel algorithms. To speed up the simulation time of cycle based simulation, we will also present a technique of fast cycle based simulation that utilizes the bit-level parallelism in a computer word. We have done the numerical performance analysis of the four algorithms, and implemented a VHDL simulator based on one of them. Our parallel simulation technology benefits from lower communication overhead and better load balancing. In fact, one of our algorithms doesn''t need any communication at all. The performance analysis and the experiment results show great improvement of this distributed logic simulation both on simulation time and system scalability. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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