The Research of Scaling Theory for Silicon-On-Insulator MOSFET's
| Autor: | Zi-Ping Chen, 陳子平 |
|---|---|
| Rok vydání: | 1999 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 87 A scale down theorem for an ultra-thin film SOI (Silicon-On-Insulator) MOSFET is studied in this thesis. First, we build an improved analytical model of the threshold voltage shifting and subthreshold factor with consideration about Vds bias effect by solving 2-D Poisson’s equation. Our improved model of the threshold voltage shifting can get more accurate result compared to the conventional one without adding any fitting parameter, so as the improved model of the subthreshold factor. Second, we propose a new scale down parameter α and set a design guideline for a small geometry SOI device. The new scale down parameterαis defined as α≡L/λ rather thanα≡L/2λ[26-27] and considers both threshold voltage shifting ΔVth and subthreshold factor S that having strong impact with SOI geometry. Using the new definition the curves, ΔVth vs.α and S vs. α with respect to different channel length, produced were overlapped rather than splinted. According to these results, we can design device structure without any limited size after the scale down parameter was decided (α≧6). Thus, it can help us to build a guideline for designing a small geometry device. The guideline was summarized in following steps:(1) Define the front gate oxide thickness tof (tof≧4nm) and buried oxide thickness tob (tob≧400nm). (2) Select a suitableα (α≧6). (3) Use our formulas to calculate a suitable silicon film thickness tsi after decided channel length L. Our objective, ΔVth |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|