Synthesis and Fault Models of Multi-Valued Logic and Operational Amplifier
| Autor: | Yeong-Jar Chang, 張永嘉 |
|---|---|
| Rok vydání: | 1999 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 87 This dissertation studies design and synthesis for multiple-valued logic (MVL) circuits, fault models of MVL circuits, as well as the fault model for the operational amplifier. On design and synthesis, two schemes to synthesize MVL circuits are proposed: one is for the hybrid-mode circuits, the other is for the voltage-mode circuits. For both circuits, IC chips were fabricated to demonstrate their functions. The result indicates the MVL circuits synthesized by our methods have all the advantages of higher speed, lower power and smaller area than that synthesized by traditional methods. Compared with the binary circuits, the hybrid-mode circuit under the comparable speed of the binary circuit has 40% area reduction, and the voltage-mode circuit has 60% area reduction but consumes only about one-tenth of the dynamic power. This research demonstrates that the MVL hybrid mode CMOS circuit is more suitable to the addition operation and the MVL voltage mode CMOS circuit is more suitable to the lower power application. Based on the above criteria, a hybrid mode CMOS adder and a voltage mode CMOS multiplier were designed and realized in a chip through CIC (Chip Implementation Center), and their functions were verified through measurement. On the testing of the MVL, a more reasonable and more practical fault model was proposed. Analyzing the proposed circuits, we discover that: at the transistor-level, three faults, i.e., current mirror mismatch, current source variation and switch stuck-at faults can describe the faulty behavior of the MVL circuits; and at the logic level, three faults, i.e., literal window shift, constant variation and input variation can describe the faulty behavior of the MVL systems. The test patterns derived from the above fault model are more effective and reasonable than those derived from the traditional stuck-at fault model to test the MVL circuit. Since an MVL circuit can be viewed as an intermediate circuit between a binary circuit and an analog circuit. The practice adopted in testing of the MVL circuit can be considered to be applied to testing the analog circuit. This dissertation also studies the application of the testing of MVL circuit to the testing of the analog circuit, such as the analog fault simulation based on the MVL simulation. Since the operational amplifier (OP) is the most primitive and important building element for an analog circuit, hence, the faulty behavior of the closed-loop OP was first investigated and then a new fault model which is much simpler but without losing its validity than the traditional fault model is proposed. The proposed fault model is an offset fault model which lumps the finite gain, finite input resistance and the non-zero output resistance into an input offset of the OP which is considered to be an ideal. Moreover, the fault model also contains elements which is the limited-current fault to describe the output distortion of the OP when too large a current is required to be drawn from the OP due to too small an external resistance or too large an external capacitance is connected to the OP or a signal of too a high speed is applied to the OP. This offset fault model is verified to be able to cover 92.5% catastrophic faults and 100% parametric faults. For this fault model, when used in fault simulation for the linear analog circuits composed of closed-loop OPs and non-bridged type passive elements, much faster speed improved can be obtained. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|