Research on Mixed-Mode VLSI Chip Design for PH-Meter System Application
| Autor: | Jin-Sheng Hsieh, 謝晉昇 |
|---|---|
| Rok vydání: | 1999 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 87 The major objective of this thesis is to design, research and implement the integrated circuit of digital type pH meter in mixed-mode VLSI design method. All of the design flow, such as circuit theorem, system specification constitute, circuit design and simulation, layout, post layout simulation and measure result are introduced in this thesis, too. The ISFET pH sensor need a constant voltage and constant current source to be its work condition. The output (VGS) of pH sensor will be linearity because of the constant voltage and current source, therefor the main function of analog read out circuit is providing constant voltage, current and read out the signal of pH sensor. In order to fit the working range of analog/digital converter, level shift circuit adjusts the signal to be a proper analog signal. Analog/digital converter converts the analog signal to a 8 bits digital data. Because the 8 bits digital data is absolute, we need a relative reference point to make the data to be relative. Calibration circuit will load the data of pH4 and pH7 to be the reference points, change unlinearity signal to linearity signal and adjust offset value to output to decoder circuit. The decoder circuit decode the data of calibration circuit to be B.C.D code and B.C.D code is decoded to be seven segment control code then. The implemented pH meter works in the condition of single power 5V, 1KHz clock frequency, The error value is 0.36pH~-0.2pH In the test process in pH2~pH11. The technique that we implement is UMC 0.5 m CMOS DPDM( Double Poly Double Mental ) . |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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