Design of a BP-based Neural Net Processor for Computing the BPN Algorithm
| Autor: | Lue Wang-Chi, 劉萬吉 |
|---|---|
| Rok vydání: | 1998 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 86 This thesis is related to the design and implementation of a BP-based neural net processing system for increasing the computational performance of the BPN algorithm.The training process included in the BPN algorithm requires large amount of matrix multiplication. Therefore, a SIMD-Systolic array processor has been developed to solve such a computational bottleneck. This processor is based on a VLSI array processing chip which has been designed and fabricated by using 0.6um CMOS technology. Currently, it is integrated with Pentium-100 computer through PCI local bus, and, operates at 1MHz. To multiply two matrices of sizes 8×8 and 8×256, this processing system runs 4.6 times faster than software running on Pentium-100 computer. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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