Design and Analysis of CMOS Flash A/D Converter Implemented with Chopper-Type Comparator
| Autor: | Hsiang-Lin Hsu, 許祥麟 |
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| Rok vydání: | 1994 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 82 This thesis describes a Flash A/D converter we have designed. The A/D converter is designed with the 0.8-um DPDM CMOS process technology and has been verified by the HSPICE simulator under the requirements of eight-bit resolution and 50 million samples per second. Finally, this flash A/D converter has been completely implemented in a single chip with active area of 1740um x 1280um. For a flash A/D converter, its operating speed and power consump- -tion are determined by that of the comparator in it. Although the chopper-type comparator with its simple circuit structure is an inherent low power amplifier relative to the complicate differential type, we still need to be engaged in maximizing the signal-to-noise ratio to overcome its drawback of poor noise immunity. As expected, such a task can be achieved by optimizing the capacitance of the AC signal coupling capacitor and the transistor size of the inverting amplifier, the autozero, and the sampling switches. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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