| Popis: |
imulated Annealing (SA) is a popular placement heuristic used in many commercial and academic FPGA CAD tools. However, SA placement requires high runtime to produce good quality results. As FPGAs continue to grow in size, runtime has become more crucial for SA-based placers. This thesis aims to improve SA placement by making it more efficient in two key areas for large heterogeneous FPGAs: move generation and placement cost evaluation. This work shows that by using Median Region moves for heterogeneous architectures, the wirelength is reduced by 5% while maintaining the same critical path delay. We also show that by using a better search data structure the runtime is improved by 5%. A new Timing Cost function incorporating Delay Budgets is introduced in this work, and it improves the circuit speed by 4% with no degradation in wirelength. This cost function also performs better on large circuits, where it improves circuit speed by 7%. |
