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As demand for computational processing power continues to rise, chip manufacturers have recently shifted from raising clock rates towards increasing processing core counts, heralding the era of multi-core processors. While available chip real estate continues to grow due to shrinking transistor dimensions as predicted by Moore's law, the number of processing cores is anticipated to reach into the hundreds and even thousands, co-located on individual silicon dies. Supporting these future ``many-core" processors requires high bandwidth, low latency, and power efficient on-chip networks with minimal area overhead to facilitate core-to-core and core-to-memory communication. Increasing network complexity has revealed limitations of traditional electrical interconnects and has motivated research in emerging technologies such as silicon nanophotonics for future interconnects. In this thesis silicon nanophotonic technology is explored for implementing high performance core-to-core and core-to-memory interconnects. Two interconnect architectures are presented, a bandwidth reconfigurable on-chip interconnect for intra-chip communication, CLAP-NET, and a low power, high performance inter-chip interconnect, Cross-Chip. |
