Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length
| Autor: | Sreenivasulu, V. Bharath, Narendar, Vadthiya |
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| Zdroj: | In AEUE - International Journal of Electronics and Communications July 2021 137 |
| Databáze: | ScienceDirect |
| Externí odkaz: |
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