Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process
| Autor: | Zhang, Qingzhu, Tu, Hailing, Zhang, Zhaohao, Li, Junjie, Wei, Feng, Guilei Wang, Han, Jiaohao, Zhao, Hongbin, Zhang, Yongkui, Li, Yongliang, Wu, Zhenhua, Gu, Jie, Xu, Renren, Bai, Guibin, Xu, Gaobo, Wei, Qianhui, Fan, Yanyan, Yan, Jiang, Li, Bo, Xu, Qiuxia, Yin, Huaxiang, Wang, Wenwu |
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| Zdroj: | In Materials Science in Semiconductor Processing January 2021 121 |
| Databáze: | ScienceDirect |
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