III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications
| Autor: | Tripathy, Manas Ranjan, Singh, Ashish Kumar, Baral, Kamalaksha, Singh, Prince Kumar, Jit, Satyabrata |
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| Zdroj: | In Superlattices and Microstructures June 2020 142 |
| Databáze: | ScienceDirect |
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