A novel technique exploiting C–V, G–V and I–V simulations to investigate defect distribution and native oxide in high-κ dielectrics for III–V MOSFETs

Autor: Sereni, G., Larcher, L., Vandelli, L., Veksler, D., Kim, T., Koh, D., Bersuker, G.
Zdroj: In Microelectronic Engineering 1 November 2015 147:281-284
Databáze: ScienceDirect