Gate-last integration on planar FDSOI for low-VTp and low-EOT MOSFETs
Autor: | Morvan, S., Andrieu, F., Leroux, C., Garros, X., Cassé, M., Martin, F., Gassilloud, R., Morand, Y., Le Royer, C., Besson, P., Roure, M.-C., Euvrard, C., Rivoire, M., Seignard, A., Desvoivres, L., Barnola, S., Allouti, N., Caubet, P., Weber, U., Baumann, P.K., Weber, O., Tosti, L., Perreau, P., Ponthenier, F., Ghibaudo, G., Poiroux, T. |
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Zdroj: | In Microelectronic Engineering September 2013 109:306-309 |
Databáze: | ScienceDirect |
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